1. Technical Field
The present application relates, in general, to semiconductor devices and, more particularly, to vertical-channel junction field effect transistors (VJFETs) having buried gates and to methods of making these devices.
2. Background of the Technology
Silicon Carbide (SiC), a wide band-gap semiconductor material, is very attractive for use in high-power, high-temperature, and/or radiation resistant electronics. SiC power switches are logical candidates for these applications due to their excellent material physical properties such as wide energy band-gap, high breakdown field strength, highly saturated electron drift velocity and high thermal conductivity compared to the conventional silicon counter part. In addition to the above advantages, SiC power devices can operate with lower specific on-resistance than conventional silicon power devices [1].
JFETs in SiC are especially attractive for high power applications thanks to the inherent stability of their p-n junction gate, which is free from gate oxidation problems concerning channel mobility in MOS structure and high-temperature reliability issues in MESFETs having metal-semiconductor Schottky barrier.
Because of the fundamental differences in material properties and processing technologies, traditional Si or GaAs microelectronics technologies in JFETs can not be easily transferred to SiC. A number of reports of SiC JFETs have appeared in the last decade (e.g., [2-4]). An example of a vertical channel JFET employing a recessed gate structure can be found in U.S. Pat. No. 4,587,712 [5]. An example of a lateral JFET formed in SiC can be found in U.S. Pat. No. 5,264,713 [2]. Enhanced-mode JFET for digital ICs with resistive load has been reported in 2000 [6]. JFET-based ICs can also be implemented in either complementary n-type and p-type channels as disclosed in U.S. Pat. No. 6,503,782 [7] or enhanced-depletion (n-type channels) forms. SiC JFETs have proven to be radiation tolerant while demonstrating minimal threshold voltage shift over a wide temperature range [8, 9].
Most of the obstacles to low-cost volume manufacturing can be traced back to the gate-level process steps. In addition, the p-type gate contact can be difficult to fabricate in SiC because of the large band-gap of SiC. In fact, low resistivity contacts to p-type SiC have only been formed on heavily doped p-type SiC.
The VJFET (i.e., a JFET with a vertical channel structure) can be fabricated smaller than a JFET with a lateral channel structure, which leads to lower cost in volume manufacturing of discrete transistors, and can also increase the packing density in large scale integrated circuits. To obtain a vertical channel in SiC VJFETs, ion implantation is often used to form the P+ gate region [8-10]. It can be difficult, however, to precisely control the channel length by ion implantation because of a combination of uncertainties on actual depth profile of implantation tail, defect density, redistribution of implanted ions after thermal annealing, and ionization percentage of dopant atoms and point defects under different bias and/or temperature stress.
Alternative methods to form a vertical channel have also been employed. One method is to selectively grow P+ gate regions epitaxially as taught in U.S. Pat. No. 6,767,783 [11].
There still exists a need, however, for improved high volume, low cost manufacturing methods for VJFETs that allow for the precise control of channel length during manufacture.